This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-097115, filed Mar. 29, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device comprising setting the exposure amount and the focus value in forming a pattern by transferring a circuit pattern on a mask onto a resist film.
2. Description of the Related Art
In the photolithography process in manufacturing a semiconductor integrated circuit, an apparatus called an exposure apparatus for performing pattern exposure is used. An example of the exposure apparatus is a reduction projection exposure apparatus (stepper or scanner). In this reduction projection exposure apparatus, light from the light source is transmitted through a mask on which an exposure pattern is drawn so that the pattern is reduced by the optical system and projected onto a wafer.
In pattern formation for transferring a pattern drawn on the mask onto the wafer, the minimum transferable pattern size must be reduced. On the basis of the optical imaging theory, letting NA be the numerical aperture of the projection optical system, and xcex be the exposure wavelength, a resolution (line width) R and depth of focus DOF are given by well-known equations:                     R        =                  k1          ⁢                      xe2x80x83                    ⁢                      λ                          N              ⁢                              xe2x80x83                            ⁢              A                                                          (        1        )                                          D          ⁢                      xe2x80x83                    ⁢          O          ⁢                      xe2x80x83                    ⁢          F                =                  k2          ⁢                      λ                          N              ⁢                              xe2x80x83                            ⁢                              A                2                                                                        (        2        )            
where k1 and k2 are process coefficients.
These are called Rayleigh equations and used as criteria to evaluate the imaging performance of a projection exposure apparatus. In response to the demand for shrinkage in feature size of patterns, the exposure wavelength is shortened, the numerical aperture of a projecting lens is increased, and simultaneously, the process is improved. However, since the recent demand for shrinkage in feature size of device patterns is stricter, a sufficient process margin for the exposure margin or depth of focus can hardly be obtained, resulting in a decrease in yield.
For photolithography with a small process margin, great importance is being attached to error distribution (error budget) and accurate analysis of error that consumes the process margin. For example, even when a wafer is exposed at the supposedly same set exposure to form a number of chips, the effective appropriate exposure varies due to PEB (Post Exposure Bake), nonuniformity of development in the wafer surface, or a variation in resist film thickness in the wafer surface, resulting in a decrease in yield. Hence, demand has arisen for an exposure and focus control method that effectively uses a small process margin, accurately monitors and feeds back or forward the exposure and focus position to prevent a decrease in yield. At the same time, error factors that consume the process margin must be accurately analyzed in units of process units, and major error factors must be removed on the basis of the analysis result.
Two methods have been reported as exposure control methods. As the first method, the exposure is obtained on the basis of the measurement result of a resist pattern line width or latent image pattern line width. As the second method, the effective exposure is obtained on the basis of measurement data of diffraction light intensity that is obtained by irradiating a resist pattern line width or latent image pattern line width with collimated light.
However, the pattern line width changes depending on not only the exposure but also the focus position. For this reason, it cannot be determined from the measurement result obtained by the above normal methods whether the line width is affected by a variation in exposure value or focus position, or both of them.
On the other hand, two methods have been reported as focus monitor methods. As the first method, the focus position is measured using a variation in size of a monitor mark after exposure due to defocus. As the second method, a variation in focus position is measured as a position shift of a pattern using a mark of phase shift mask type.
In the conventional focus monitor methods, even when the focus shift amount can be obtained and feedback to the focus set value, a variation in appropriate exposure value cannot be taken into consideration only using these marks. Hence, the exposure margin cannot be effectively used while suppressing the process variation factors.
The above problems become more serious for finer patterns with a smaller focus margin, or isolated patterns having a smaller feature size. The process variation factors cannot be completely suppressed only by monitoring one of the exposure and focus position, and feedback the obtained measurement result to the set exposure, PEB temperature, development time, and the like of the exposure apparatus.
According to one embodiment of the present invention, there is provided a method of manufacturing a semiconductor device involving a method of controlling an apparatus for manufacturing a semiconductor device, the method comprising setting the exposure and the focus position in forming a pattern by transferring a circuit pattern formed on a mask by an exposure apparatus onto a resist film formed on a wafer, comprising:
coating the wafer with a resist film; applying a first heat treatment to the resist film; applying a first cooling treatment to the resist film subjected to the first heat treatment; the heating condition for the second heat treatment, setting an exposure and a focus position at prescribed values and applying an exposure treatment to the resist film to which is applied a first cooling treatment by using a mask in which is arranged a monitor mark including at least one of an exposure monitor mark for detecting the effective exposure on the wafer and a focus monitor mark for detecting the effective focus on the wafer so as to form a latent image corresponding to the monitor mark in the resist film; applying a second heat treatment to the resist film having the latent image formed therein; applying a second cooling treatment to the resist film having the second heat treatment applied thereto; applying a developing treatment to the resist film having the second cooling treatment applied thereto so as to form a monitor pattern corresponding to the latent image; measuring the state of the latent image of the monitor mark or the state of the monitor pattern at least once any time after the exposure treatment, after the second heat treatment, during the second cooling treatment, after the second cooling treatment, during the developing treatment, and after the developing treatment; obtaining at least one of the effective exposure and the focus position in the exposure treatment applied to the resist film based on the measured state of the latent image of the monitor mark or monitor pattern; calculating at least one of the difference between the optimum exposure in performing an exposure by using the mask and the set value and the difference between the optimum focus position and the set value from at least one of the obtained effective exposure and focus position; and changing at least one of the set value of the focus position, the set value of the exposure, the heating condition for the first heat treatment, the developing condition for the developing treatment, the residence time between the completion of the exposure treatment and the start-up of the second heat treatment, the residence time between the completion of the second heat treatment and the start-up of the second cooling treatment, the residence time between the completion of the second cooling treatment and the start-up of the developing treatment, the residence time between the completion of the resist film coating and the start-up of the heat treatment, the residence time between the completion of the first heat treatment and the start-up of the first cooling treatment, and the residence time between the completion of the first cooling treatment and the start-up of the exposure.